PCIe/USB/SATA PHY Appilcation example | Renesas
USB 2.0 Full High Speed Solution | NXP Semiconductors
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB2 Controller
USB 2.0 Full High Speed Solution | NXP Semiconductors
HSIC USB 2.0 PHY IP
USB 2.0 Device Controller IP Core (USB20SF)
USB2.0 PHY – Silicon Library Inc.
EETimes - Partitioning hi-speed USB systems
GOWIN Releases USB 2.0 PHY and Device Controller IP for Their FPGA Products | Civil + Structural Engineer magazine
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 Solutions | Arasan Chip Systems
Figure 4 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USB2.0 Transceiver IC - USB3318 - COM-09631 - SparkFun Electronics
Standalone USB Transceiver Chip - EEWeb
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
USB 2.0 OTG IP Core | Arasan Chip Systems
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
The USB 2.0 Device IP core | Arasan Chip Systems
ULPI - Kcchao
USB 2.0 PHY for SoC Designs | Cadence IP
USB 2.0 PHY Verification
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB2 PHY | Cadence
